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Non-IT Course

VLSI

Learn the VLSI design flow from logic synthesis through floorplanning, routing, and signoff.

VLSI Design FlowLinux BasicsLogic SynthesisStatic Timing AnalysisFloorplanning & PlacementClock Tree SynthesisRouting & Signoff
About This Course

VLSI

A structured walkthrough of the complete VLSI physical design flow — from logic synthesis and static timing analysis through floorplanning, placement, clock tree synthesis, routing, physical verification, and signoff.

Course Curriculum

1
Introduction to VLSI
What VLSI is, history, industry applications, the VLSI design flow, and an EDA tools overview.
2
Linux Commands for the VLSI Flow
Basic terminal usage, file/directory commands, permissions, and commands used in the VLSI flow.
3
Logic Synthesis
RTL-to-gate-level synthesis, synthesis constraints, timing concepts, and area vs. speed trade-offs.
4
Static Timing Analysis (Pre-layout)
Setup and hold checks, critical path analysis, clock definitions, and basic STA reports.
5
Floorplanning
Core and die area, macro placement, power planning, and I/O placement basics.
6
Placement
Standard cell placement, congestion analysis, and optimization techniques.
7
Clock Tree Synthesis (CTS)
Clock tree concepts, clock buffering, and skew/latency control.
8
Routing
Global routing, detailed routing, and DRC considerations.
9
Physical Verification
DRC checks, LVS verification, and antenna checks.
10
Signoff & Capstone Project
Final STA, IR drop and EM checks, tapeout readiness, and a review project.
Career Outcomes

After Completing This Course

🎯VLSI Design Engineer (Junior)
🎯Physical Design Trainee
🎯EDA Tools Associate

Course Details

Fee₹4,999
Duration16+ Hrs
ModeOnline (live instructor-led)
EligibilityECE/EEE engineering students or graduates
CertificateYes, on completion
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